1. Field of the Invention
The present invention relates to a semiconductor device formed using a semiconductor layer provided on an insulating surface, and particularly a miniaturization technique for a field effect transistor.
2. Description of the Related Art
A method is known, in which miniaturization of a thin film transistor (hereinafter, also referred to as “TFT”) that is one kind of filed effect transistors is attempted by shortening a channel length represented as a distance between a source and a drain in order to achieve high performance. This is a method in which high-speed operation is attempted by shortening a traveling distance of carriers flowing through a channel of the transistor.
However, when the channel length is shortened, a phenomenon that threshold voltage is changed and leak current is increased between the source and the drain in a weak inversion state, which is a so-called short-channel effect, becomes prominent. Thus, a method is known, in which an impurity concentration in a channel formation region is increased to suppress expansion of a depletion layer, so that the short-channel effect is suppressed.
For example, a TFT is known, in which a gate electrode layer is formed to have two layers, and the width of a lower layer is smaller than that of an upper layer to reduce gate capacitance, so that the short channel effect is suppressed (for example, see Reference 1: Japanese Published Patent Application No. 2006-41265).